1. Field of the Invention
The present invention relates to a data discriminating circuit, which performs signal discrimination in a receiver of a digital signal transmission system, and an optical receiver using the data discriminating circuit.
2. Description of the Related Art
Due to the development of the optical communication technology, attention is paid to a so-called fiber to the home (FTTH) or the like and study has been made on this system. This FTTH system implements optical transmission technology to lay optical fibers in subscriber systems as well as the trunk line system to thereby ensure wide-band information transmission of dynamic images or the like. An important factor in implementing optical transmission technology in a subscriber system is that the implementation should be accomplished at a low cost. It is therefore necessary to design the structures of the transmitter and receiver considerably simpler than those used in the trunk line system, thus making the adjusting components as few as possible.
In the receiving section, particularly, it is necessary to properly adjust the timing relation (phase relation) between data and a discrimination clock in the data discriminating circuit which converts an optical signal, sent over an optical fiber, into an electric signal and then discriminates digital "1" or "0."
It is also important to simplify this circuit portion by LSI or the like to thereby eliminate the need for separate adjustments as much as possible. Even in designing the circuit into LSI, the structure should be made as simple as possible to meet some requirements for the implementation of the data discriminating circuit in the subscriber system, such as reduction of consumed power and reduction of the circuit scale.
FIG. 16(a) illustrates the structure of a conventional optical receiver serving as an optical repeater that executes data transmission between terminal devices in the trunk line system. In the conventional optical receiver, an optical signal transmitted over an optical fiber 20 is photoelectrically converted into an electric signal by a light-receiving element 21. This electric signal is amplified to a discriminatable level by an equalizer/amplifier 22.
At the same time a discrimination clock is extracted from the received signal by a timing circuit 24, and this clock is input together with the amplified signal to a discriminating/reproducing circuit 23.
At this time, the phase relation between the amplified signal and the clock from the timing circuit 24, which are input to the discriminating/reproducing circuit 23, is not stable due to a variation in transmission time in the individual circuits or other factors. To keep the proper phase relation, some kind of adjusting means should be provided to adjust the phase relation.
In many optical repeaters of the above type, a coaxial cable 25 or the like is used to connect the timing circuit 24 to the discriminating/reproducing circuit 23 and the length of the coaxial cable 25 is properly adjusted for each receiver to thereby provide the desired phase relation.
Due to the recent development and improvement of IC technology, there appears an optical receiver equipped with a circuit for automatically adjusting the phase relation. FIG. 16(b) exemplifies such an automatic phase adjusting circuit (which has been proposed by Peter Cochrane et al. in IEEE Journal on Selected Areas in Communications, Vol. SAC-4, No. 9, Dec. 1986).
In the circuit shown in FIG. 16(b), a signal before discrimination and a signal after discrimination are respectively input to S-R latches 26 and 27. The signal pulses output from those S-R latches are integrated, and the level of the resultant signal is then compared with a reference level. The result of the comparison is fed back to a voltage-controlled phase shifter 28 to keep the phase of the clock at a predetermined value.
If the optimal phase relation changes in the circuit shown in FIG. 16(b) due to the temperature characteristic of the circuit or the time-dependent characteristic of the circuit, a constant phase relation can be maintained by the feedback control unlike in the case where a coaxial cable is used as shown in FIG. 16(a).
This automatic phase adjusting circuit is designed to perform analog control on the clock phase to keep the proper phase. This circuit is complicated and increases the consumed power in many cases. It is therefore difficult to adapt this circuit to the subscriber system unless the circuit structure is simplified and the consumed power is reduced.
As described above, the transmission length in the subscriber system is very short (about 1 to several Km) as compared with that in transmission between terminal devices. Therefore, the optical level of the input to the optical receiver can be increased systematically. Accordingly, the data discriminating circuit can have a large phase margin to secure the desired characteristic in the received signal. Instead of the aforementioned analog phase control, therefore, a plurality of clocks having different phases may be prepared and a clock of a particular phase may be selected from those clocks to acquire the desired discrimination characteristic.
An example of the structure of such a data discriminating circuit is disclosed in Japanese Unexamined Patent Publication Nos. 233850/1989 and 188050/1989. In the former Japanese Unexamined Patent Publication No. 233850/1989, the same data is discriminated using two types of clocks having slightly different timings. When the discrimination results differ from each other, it is considered that the clock phase is not the proper one and the clock phase is inverted.
In the latter Japanese Unexamined Patent Publication No. 188050/1989, a clock with a frequency twice the data transmission rate is prepared. When data is input, a T-FF (flip-flop) is reset at its rising edge to frequency-divide the double-frequency clock, and the data is discriminated with a clock having a slight delay from the rising of the data.
In both techniques, the data discriminating circuit itself can be constituted of a logic circuit, for example, a gate array, thus ensuring the simplification of the circuit and reducing the cost.
According to the technique disclosed in Japanese Unexamined Patent Publication No. 233850/1989, even when data of "0" is erroneously discriminated as "1" with both types of clocks, either clock is considered as the proper one. Further, the discrimination result is influenced by the time difference between the two types of clocks and the time difference occurring at the time the input data is distributed to two discrimination sections (D-FF), very delicate timing design is required.
As the technique disclosed in Japanese Unexamined Patent Publication No. 188050/1989 deals with a double-frequency clock, a clock having a frequency twice the transmission rate of the transmission system should be prepared. Therefore, the general structure of the system lacks affinity, and this system should have a clock multiplication circuit, thus eventually resulting in the enlargement of the circuit scale.
According to the prior arts, therefore, it is not possible to achieve the system which reliably and surely performs data discrimination while properly keeping the phase relation between data and the clock. Such a system, if accomplished, should suffer the complicated circuit and the large circuit scale.